1. Field of the Invention
The present invention relates to a method for DRAM fabrication, and more particularly, to the cell pass transistor design in DRAM fabrication.
2. Description of the Prior Art
As circuitry density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One recent technique finding greater application in achieving reduced transistor size is to form field transistors with thin films, which are commonly referred to as "thin film transistor" (TFT) technology.
FIG. 1A shows a top view in the fabrication of a conventional MOS structure, and FIGURE 1B shows a flowchart in the fabrication of the conventional MOS structure. Conventionally, a resist layer is patterned and first P-type ions are then implanted to form a well implantation region in the silicon substrate 100. Moreover, second P-type ions are implanted to form a field implantation region in the silicon substrate 100. Consequentially, third P-type ions are implanted to form a punchthrough implantation region in the silicon substrate 100. Finally, fourth P-type ions 110 are implanted to form a threshold implantation region in the silicon substrate 100. The threshold implantation region is formed to implant a dosage between about 1.0 E 13-1.0 E 18 atoms/cm.sup.2. Finally, the resist layer is removed. When DRAM technology enters 0.18 .mu.m and below, the substrate convention of the cell pass transistor substrate concentration (Nsub) must increase as high as 1.0 E 18 to control cell transistor short channel effect. But this high cell pass transistor substrate concentration (Nsub) will induce more junction leakage for P/N junction, decreasing the refresh time capability.